Altium

Design Rule Verification Report

Date: 05/07/2023
Time: 03:15:02
Elapsed Time: 00:00:04
Filename: C:\VIRGIL\AAA__JOB\ALTIUM\STM\Projets\MB1918C\BASE\MB1918C\01-Design-sources\Altium_Designer\MB1918.PcbDoc
Warnings: 0
Rule Violations: 0

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=0.12mm) (All),(All) 0
Clearance Constraint (Gap=0.13mm) (InNetClass('NC__USB-90R')),(All) 0
Clearance Constraint (Gap=0.22mm) (InNetClass('NC_S50R_FLASH')),(All) 0
Clearance Constraint (Gap=0.12mm) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Short-Circuit Constraint (Allowed=Yes) (InPadClass('PADS_LINK_CC')),(InPadClass('PADS_LINK_CC')) 0
Un-Routed Net Constraint ( (All) ) 0
Width Constraint (Min=0.12mm) (Max=10mm) (Preferred=0.12mm) (All) 0
Width Constraint (Min=0.14mm) (Max=0.17mm) (Preferred=0.17mm) (InNetClass('NC_S50R_FLASH')) 0
Routing Layers(All) 0
Routing Via (Templates Used To Check Via: v60h30m35mx35) (All) 0
Routing Via (Templates Used To Check Via: v40h15m20mx20) (WithinRoom('RoomDefinition_STLink')and TouchesRoom('RoomDefinition_STLink')) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.13mm) (Max=0.13mm) (Prefered=0.13mm) and Width Constraints (Min=0.11mm) (Max=0.15mm) (Prefered=0.15mm) (InDifferentialPairClass('PC__USB-90R')) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Hole To Hole Clearance (Gap=0.42mm) (InDrillLayerPair('Top Layer - Bottom Layer')),(InDrillLayerPair('Top Layer - Bottom Layer')) 0
Net Antennae (Tolerance=0mm) (All) 0
Component Clearance Constraint ( Horizontal Gap = 0mm, Vertical Gap = 0mm ) (All),(All) 0
Height Constraint (Min=0mm) (Max=40mm) (Prefered=40mm) (All) 0
Height Constraint (Min=0mm) (Max=5mm) (Prefered=5mm) (OnBottomLayer and WithinRoom('HMAX 5MM')) 0
Total 0